FPGA Implementation of an Improved Turbo Decoding Algorithm

In order to effectively reduce Turbo decoding complexity in hardware implementation and reduce its resource consumption, an improved Turbo decoding algorithm named improved-Max-Log-MAP is proposed. This new algorithm is a compromise algorithm between Log-MAP algorithm and Max-Log-MAP algorithm and it's more suitable for parallel calculation. This new algorithm replaces the multi-input operation-max<sup<*</sup<(·) with the operation-max which only calculates the maximum value while the algorithm still uses the operation-max<sup<*</sup<(·) in the case of two input variables. The simulation results indicate that improved-Max-Log-MAP algorithm's complexity is approximate to Max-Log-MAP algorithm and while the performance is approximate to Log-MAP algorithm. When Turbo codec using the new algorithm is implemented on FPGA and applied to LEO satellite communication systems, it obtains excellent performance with low complexity and resource consumption, which can help reduce power consumption and size of LEO satellite handheld communication terminal.