A Small-Area Design of Radix-3 Butterfly Unit

A new technique for radix-3 FFT butterfly unit based on floating-point operation is proposed. The aim of the new design is to reduce the hardware resources. First, compatible scaling is used to solve the multiplication. Let the scale factor of √3 be 2<sup<23</sup<, so the multiplication with √3 is replaced by several fixed-point additions. By theoretical analysis, the proposed method decreases the numbers of adders and registers. By contrast, the proposed design reduces one fixed-point adder and two 48-bit registers. In additional, a structure of radix-3 FFT butterfly unit is adopted and in this structure, the number of multiplications with a real data is reduced from 4 to 2. Experimental results show that the proposed method indeed reduces the hardware resources, which plays an important role in decreasing the resources of radix-3 FFT.