Low-Latency Decoder for Quasi-Cyclic LDPC Codes Based on FPGA

A hardware architecture scheme of low-latency decoder for quasi-cyclic LDPC (QC-LDPC) codes is proposed using Min-Sum decoding algorithm. It takes the advantages of configurable embedded memory in FPGA and pipelining operational mode to improve the throughput of a decoder for QC-LDPC codes. The decoding time complexity is only about 2 times the size of the zoom factor of quasi-cyclic parity check matrix. Compared with non-pipelining decoding structure, the decoding latency is reduced to the original 1/7 without increasing logical resources.