Design of MD5 High-Speed Models on FPGA

In order to improve the performance of MD5 on FPGA, the design concept based on dataflow was proposed. At the design phase, it can assess effectively the specific FPGA, the expected system performance and the specific complex algorithms. Three models of MD5 round were put forward and one of the models was chosen to do experiment. The experimental results indicate that the designed MD5 algorithm could increase efficiently the throughput up to 66.56 Gbit/s.