Digital Post-Calibration and Design of a 5 bit 1.5 GHz Flash ADC

This paper presents a designed 1.5 GHz 5 bit flash ADC, in which an optimized track-and-hold circuit and dynamic comparator are adopted to enable high operating frequency of the flash ADC. Simulation results show, the SNDR of the presented ADC is 24.04 dB and the spurious-noise-free dynamic range (SFDR) is 29.97 dB when input signal is at the Nyquist frequency. To improve the performance of the ADC, a digital post calibration model was established based on Volterra series. The comparison results indicate that, with the role of calibration, the harmonics of ADC output have decreased, the SNDR and the SFDR is increased by 4.91 dB and 6.94 dB respectively, which means the effective number of bits (ENOB) is increased by 0.82 bit.