Design of FFT Processor Based on Grade-Memory and Parallel-Computation

The improved FFT arithmetic based on grade-memory and parallel-computation is proposed and studied. It can reduce the power consumption by decreasing the RAM's writing-reading numbers as well as reduce the execution time by parallel-computation. A 4 096-point FFT processor has been designed using the new arithmetic and the improved radix-4 butterfly. The processor was implemented by SMIC 0.18 μm CMOS technology and the core area of the chip was 9 mm<sup<2</sup<. In the slow corner condition, the post-layout simulation shows the highest frequency is 192.3 MHz, the power consumption is 422 mW@100 MHz and the minimal execution time is 67.92 μs.