DC-Offset Cancellation in CMOS Direct-Conversion Receiver SOC

A comprehensive method of system optimum design plus digital calibration to resolve DC-offset of CMOS direct-conversion receiver system-on-chip(SOC) is proposed. By reducing direct-current(DC) through local oscilator(LO) switch transistors in mixers and designing system layout optimally, the DC-offset resulting from transistors mismatch and self mixing of LO can be reduced in the range that digital calibration can handle. Under the low power consumption restriction, DC-offset can be controlled in an allowable range by means of digital calibration.