Efficient Implementation of an All-Adder Multiplier-Free Decimation and Compensation Filter

A novel algorithm on multiplier-free finite impulse response filter(FIR) is presented, which can be efficiently implemented to compensate the cascade integrator-comb filter passband ripple. The multiplier-free architecture is achieved by a power-of-2 digital to approximately represent the compensation filter coefficients. With this representation, multiply operation is replaced with a shift operation, which can be efficiently hardware implemented. Simulation results proved that the coefficients-approximate filter can well reach the demand of CIC compensation filter.