Design of 10 Pipeline Stages Multiplier for Double Precision Floating Point Data

A new design method of pipelined multiplier for double precision floating point data based on IEEE754 standard was proposed.The method is faced for digital signal processor with 32 bit data path.Each 64 bit operand was divided into two 32 bit data and the multiplication of significand was accomplished by 32 bit×32 bit unsigned array multipliers.By transferring partial products and their selection signals synchronously,only one 66 bit adder was used to add all four partial products.A method for rounding was also proposed.The whole operation was divided into 10 pipeline stages.The correctness and performance can be confirmed by simulation results.