FPGA Implementation of Turbo Decoder in Frequency-Hopping System

Implementation scheme of FPGA(field programmable gate array) Turbo decoder is presented.Max-Log-Map algorithm and modular design methodology is employed and the decoder is able to decode variable length Turbo codes.A Turbo decoder with variable packet length has been implemented in a Xilinx xc3s2000-4fg676 FPGA circuit.Under the condition that packet length is(1?024?bit) and iteration times is 5,the throughput of the decoder is 1.261?Mbit/s and decoding latency is 0.812?ms.The designed Turbo decoder is tested under additive white Gaussian noise and partial-band noise interference channel for its bit error rate performance.AGC(adaptive gain control) is employed under partial-band noise interference channel.Simulation results showed that performance of the decoder is improved with AGC.