Study on the Synthesis Algorithm Supporting AFTER Clauses

A study on AFTER clauses in the VHDL hardware description language is presented to improve the design efficiency of HLS system, so as to decrease manual interruption and enhance the automatism of HLS system. Through the definition of behavioral synthesis meaning of AFTER clauses, the enhanced ASAP and ALAP algorithm under AFTER clause delay time constraints is presented. The scheduling model under AFTER clause delay time constraints is also presented. The scheduling model is resolved by ILP. According to experimental results presented, an effective way to set timing constraints is offered by considering AFTER clause in high-level synthesis. At the same time, the design description style can be more acceptable to the designer, and the range of available grammar in behavioral description is expanded. The ability of forecasting synthesis result is enhanced.