The Study of High-Speed Windowed Complex FFT Processors Based on FPGA

A method of realizing high speed special FFT processor based on FPGA is presented. The processor can put the complex data into three operations in sequence: multiplying the window, performing FFT, and computing module square. Experiments prove that the design posseses four specialties. To save logic and hardware resources, the above three operations are performed by a single operation unit. As a result of adopting pipelined architecture, the processing speed is improved and the three operations including communication, calculation and storage work harmoniously. By using the block floating point algorithm, the system has the merit of high speed and high precision. TMS memory architecture requires less speed to the peripheral equipment. The design method can widely be used in high speed digital signal processing fields.