Solutions to Some Problems in the Automatic Generation of Systems Schematic Diagrams

This schematic diagram generation systerm is a sub-sytem of the VHDL language high-level logic synthesis system.It accepts the netlists abstracted from the result of logic synthesis as its input. In this paper, the level-assignment algorithm in automatic placement,the processing of feed-back loop and the track distribution in automatic routing are discussed. Some test results are given in the final part of thsi paper.