一种改进型双级捕获系统研究及其VLSI实现

An Improved Two-Stage Acquisition System and Its VLSI Implementation

  • 摘要: 针对以匹配滤波器捕获作为前端,串行滑动相关器作为后级验证的普通双级捕获算法占用资源较多并且结构复杂的缺点,提出了一种改进型的双级捕获系统.该系统在前端利用积分时间较短的串行相关器快速跳过同步阶段,在后端采用不同积分时间的串行相关器组进行验证,并采用了一种改进的(1+M/N)检测算法.最后通过FPGA+DSP的硬件平台实现了捕获电路,利用Modelsim仿真验证了改进型双级捕获算法电路中各个模块的正确性.性能比较结果表明,相比普通双级捕获系统,所提出的系统不仅可以有效降低资源使用量,而且较大地提高了检测概率.

     

    Abstract: It is known that normal two-stage acquisition algorithm is made up of matching filter as the front-end and serial sliding correlators as the back-end, which has the disadvantage of too much resource consumption. This paper proposes an improved two-stage acquisition system. The system is made up of a sliding correlator with short integration time as the front-end to skip the synchronization stage quickly and a bank of serial correlators with different integration time as the back-end for verification. Furthermore, an improved 1+M/N search detector algorithm is used in the system. At last, the acquisition circuit is implemented based on FPGA+DSP and proves the correctness of circuit modulus is proved by simulation of Modelsim. Comparative results show that the proposed system can reduce the resource consumption effectively and improve the detection probability dramatically.

     

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