Abstract: As the delay of interconnects might exceed the delay of the devices in very deep submicron realm, a novel on-chip bus structure model is proposed and designed. Multiple-valued logic (MVL) technique was used for communication between modules. Address-presetting was employed to improve the transmission efficiency. The designed structure was evaluated by ADMS simulation in a 0.18 μm CMOS technology. The results show that, corresponding to address-presetting binary bus, the number of bus is reduced significantly. In other words, with the same number of bus, the data throughput of designed bus using four-valued-logic technique could be increased by two times.