Abstract: A low-offset low-pass SCF with 1kHz cut-off frequency was designed obeying the 0.5μm two-poly three-metal (2P3M) N-well CMOS process worked out by central semiconductor manufacturing corporation (CSMC). Two measures of correlated double-sampling (CDS) and optimized switch combination were employed to improve the system performance. Simulation results show that the offset voltage has been decreased from 2mV to 23μV. The precision of signal processing system is enhanced.