Abstract: An improved efficient implementation method of digital down converter (DDC) in radio monitoring receivers is presented. Based on the sampling technique in which the sampling frequency is 4 times as high as the intermediate frequency and the use of polypahse decimation half band filter architecture, the improved architecture of high-efficiency DDC can be realized by using just one polyphase decimation half band filter to acquire the outputs of in-phase and quadrature in some sense. The improved method decreases the complexity of computation, reduces the burden of calculation and accumulated error. Resources of FPGA is saved 79% and the power consumption of the system is reduced about 60mW. One design example is given and the results proved the validity and efficiency of the improved DDC structure.