Abstract: Studies the ways with which VHDL expresses its timing and synchronization and the meanings of consistency between pre- and post- synthesis simulation of VHDL source description. For different meanings the method of synthesizing different statements is explained and realized. The ways of synthesis "loop statement", "if statement" and "case statement" are different under different VHDL timing and constraints. Synthesis of other statements related to the loop is also realized. The correctness and practicability of the method given is shown after running some typical examples.