Abstract: Presents a layout strategy based on partitioning, that can efficiently solve the problem of automatic generation of logic schematics for VLSI. A detailed partition model is discussed. Two efficient algorithms for multiple way partitioning of logic schematics are presented: the seed expansion algorithm and the iterative improvement algorithm. Experimental results show that these algorithms are not only low in their time complexity but also have high precision. They can readily be optimized and have affained fine results in their applications.