Abstract: Aim To propose a scheme for implementing FFT with FPGA in accor dance with the requirement for high speed digital signal processing. Methods The structure of FPGA and requirement of system were considered in the experiment, radix 4 algorithm of DIT and recursive structure were adopted. The group float point arithmetic operation was used in the butterfly and the array multiplier was used to realize multiplication. Results The pipeline pattern was used to ensure the system speed, it made fetching data, calculating twiddle factor, complex multiplication and DFT operation coordinate. The balance of calculation, communication and storage was realized and the bottleneck was avoided. Conclusion It demonstrates that it is a feasible method to use FPGA to realize algorithm in the high speed DSP.