Abstract: To solve the problem of large memory occupation and complicated calculation process for large-dot pulse compression of long pulse width signals in radar system, a pulse compression processing flow was proposed to avoid data transposition, and its implementation method and a delay calculation model of large-dot pulse compression processing module suitable for FPGA were put forward. Based on VPX-FPGA-D690T board, the pulse compression module was designed and realized to support 128K dots window length. The measured results show that the processing delay of the module can lower under 1700s, and it can support signals with a maximum pulse width of 4ms and a bandwidth of 10MHz. Compared with the traditional method with IP core, it can moderately increase the consumption of multiplier resources, reduce at least 50% of the processing delay and at least 40% of the memory resource consumption, improving the realizable ability for large number of points pulse compression algorithms in FPGAs.