Abstract: Multiplicative inverse operations on binary fields are widely used in cryptographic algorithms. The Itoh-Tsujii algorithm (ITA) enables multiplicative inverse operations by modulo multiplication and modulo squaring in a particular order. In this paper, a low-latency novel architecture with cascaded modulo-square modules was proposed based on the ITA algorithm and the clock cycle delay of the architecture was derived, evaluating the complexity of the cascaded modulo-square modules based on matrix weights. And then, the critical path from cascaded modulo-square modules to multiplier was optimized based on a movable internal pipeline hierarchy. Finally, experiments were carried out based on the Virtex-7 FPGA platform, which gives the Optimal Exponentiation Blocks (OEBs) for the three binary domains GF(2¹⁶³), GF(2²⁸³) and GF(2⁵⁷¹), respectively. In addition, to be fair, tests were performed on Virtex-4 FPGA platform and compared with the existing research results. The results show that the performance of the OEBs-based architecture can been improved significantly, and the latency of the proposed architecture in the three fields possesses at least 9.09%, 10.81%, and 428.95% improvement compared with the existing studies, respectively.