Abstract: In this paper, a novel code-aided maximum-likelihood (ML) carrier phase synchronization algorithm was introduced. The mean square error (MSE) of the phase estimation and the impact to the bit error rate (BER) performances were evaluated via simulations. An embedded structure of LDPC code-aided carrier phase synchronization algorithm was proposed based on FPGA to enable joint iteration between phase synchronization and decoding, to reducing the complexity and delay of the algorithm. The algorithm was implemented based on Xilinx Kintex-7 FPGA platform. The test results show that the BER performances of the proposed algorithm are very close to that of the ideal synchronization scenarios. The proposed algorithm outperforms the data-aided algorithm, it can achieve about 0.7~0.9 dB SNR gap.