Abstract: Aiming at the inter-symbol interference (ISI) caused by the multi-path interference, the inconsistency of the in-band amplitude phase of the RF device and the ADC, and the deviation of the timing sampling time in the high-speed demodulation system, a hardware efficient parallel blind equalization was proposed based on constant model arithmetic (CMA). The structure was designed with the relaxed look-ahead technique and the fast FIR algorithm. In the case where the symbol rate is much higher than the FPGA clock frequency, the blind equalization maximizes the data throughput requirements with less hardware cost by using a low complexity pipelined parallel structure. The architecture is implemented on the Xilinx XC7VX690T hardware platform and applied to the high-speed demodulation system with 600 Ms/s symbol rate, which greatly improves the quality of the signal, thus verifying the feasibility and efficiency of the algorithm.